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Features
* * * * * *
Supply Voltage up to 40V Operating Voltage VS = 5V to 18V Slew Rate Control according to LIN Specification 2.0 Supply Current during Sleep Mode Typically 10 A Supply Current in Silent Mode Typically 40 A Linear Low-drop Voltage Regulator: - Normal Mode: VCC = 5V 2%/50 mA - Silent Mode: VCC = 5V 7%/50 mA - Sleep Mode: VCC is Switched Off VCC Undervoltage Detection (10 ms Reset time) and Watchdog Reset Logically Combined at Output NRES Possibility of Boosting the Voltage Regulator with an External NPN Transistor LIN Physical Layer according to LIN Specification 2.0 Wake-up Capability via LIN Bus or WAKE Pin Wake-up Recognition TXD Time-out Timer 60V Load Dump Protection at LIN Pin Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery Adjustable Watchdog Time via External Resistor Positive and Negative Trigger Input for Watchdog 5V CMOS Compatible I/O Pins to MCU Analog Temperature Monitor Output High EMC and ESD Level Package: QFN 5 x 5 with 20 Pins
* * * * * * * * * * * * * *
LIN Transceiver with 5V Regulator and Watchdog ATA6621
1. Description
The ATA6621 is a fully integrated LIN transceiver, complying with the LIN specification, and with a low-drop voltage regulator for 5V/50 mA output and a window watchdog adjustable via an external resistor. In this QFN20 package, the voltage regulator is able to source 50 mA at VS = 18V even at an ambient temperature of 105C. The output current of the regulator can be boosted by using an external NPN transistor. This combination makes it possible to develop simple, but powerful and cheap, slave nodes in LIN bus systems. ATA6621 is designed to handle the low speed data communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud. The bus output is capable of withstanding 60V. Sleep Mode and Silent Mode guarantee a very low current consumption.
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Figure 1-1.
Block Diagram
20 VS
VCC
9 RXD
Receiver
Normal Mode
VS
7 Filter LIN
4 WAKE VCC Wake-up Bus Timer
11 TXD
TXD Time-out Timer
Slew Rate Control
Short Circuit and Overtemperature Protection
Control Unit 1 5 VCC
EN GND
Debounce Time
Standby Mode
Normal Mode 5V 2%/50 mA Silent Mode 5V 7%/50 mA Undervoltage Reset
19 18 VCC PVCC 12 NRES
TEMP
17 OUT Watchdog VCC 15 MODE 14 TM 2 PTRIG 3 NTRIG Adjustable Watchdog Oscillator 13 WD_OSC
16 GND
Internal Testing Unit
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2. Pin Configuration
Figure 2-1. Pinning QFN20
PVCC TEMP 17 GND 16 15 MODE TM WD_OSC NRES TXD 14 MLP 5 mm x 5 mm 0.65 mm pitch 20 lead 13 12 11 6 NC 7 LIN 8 NC 9 RXD 10 NC VCC 19 VS 20 EN PTRIG NTRIG WAKE GND 1
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2 3 4 5
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Description
Symbol EN PTRIG NTRIG WAKE GND NC LIN NC RXD NC TXD NRES WD_OSC TM MODE GND TEMP PVCC VCC VS Backside Function Enables the device into Normal Mode High-level watchdog trigger input from microcontroller; if not needed, leave open or connect to GND Low-level watchdog trigger input from microcontroller; if not needed, leave open or connect to VCC High-voltage input for local wake-up request; if not needed, connect to VS System ground Not connected LIN bus line input/output Not connected Receive data output Not connected Transmit data input; active low output (strong pull down) after a local wake-up request Output undervoltage and watchdog reset Watchdog oscillator For factory testing only (tie to ground) For factory testing only (tie to ground) Additional ground Chip temperature output pin 5V regulator sense input pin 5V regulator output/driver pin Battery supply Heat slug is connected to GND (pin 5)
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3. Functional Description
3.1 Supply Pin (VS)
The LIN operating voltage is VS = 5V to 18V. An undervoltage detection is implemented to disable transmission if VS falls below 5V in order to avoid false bus messages. After switching on VS, the IC starts with the Pre Normal Mode and the voltage regulator is switched on (that is, 5V/50 mA output capability). The supply current in Sleep Mode is typically 10 A, and 40 A in Silent Mode.
3.2
Ground Pin (GND)
The IC is neutral on the LIN pin in case of GND disconnection; it can handle a ground shift up to 3V for supply voltage at the VS pin above 9V.
3.3
Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads with up to 50 mA of current consumption; it is able to supply the microcontroller and other ICs on the PCB. It is protected against overloads by means of current limitation and overtemperature shutdown. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if the output voltage drops below a defined threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used with its base connected to the VCC pin and its emitter connected to PVCC.
3.4
Voltage Regulator Sense Pin (PVCC)
This is the sense input pin of the 5V voltage regulator. For normal applications (that is, when only using the internal output transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected to the output of this transistor, its emitter terminal.
3.5
Bus Pin (LIN)
A low side driver with internal current limitation and thermal shutdown, and an internal pull-up resistor in compliance with LIN specification 2.0 is implemented. This is a self-adapting current limitation; that is, during current limitation, as the chip temperature increases, the current decreases. The allowed voltage range is between -40V and +60V. Reverse currents from the LIN bus to VS are suppressed, even in case of ground shifts or battery disconnection. LIN receiver thresholds are compatible to the LIN protocol specification. The fall time from recessive bus state to dominant, and the rise time from dominant bus state to recessive are slope controlled.
3.6
Input Pin (TXD)
This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to have the LIN bus low. If TXD is high, the LIN output transistor is turned off and the bus is in the recessive state, pulled up by the internal resistor.
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3.7 TXD Dominant Time-out Function
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than tDOM > 20 ms, the LIN bus driver is switched to the recessive state.
3.8
Output Pin (RXD)
This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD, LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up structure with typically 5 k to VCC. The AC characteristics can be defined with an external load capacitor of 20 pF. The output is short-circuit protected. In Unpowered Mode (that is, VS = 0V), RXD is switched off.
3.9
Enable Input Pin (EN)
This pin controls the operation mode of the interface. If EN is high, the interface is in Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both being active. The VCC voltage regulator is operating with 5V 2%/50 mA output capability. If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible and the current consumption is reduced to IVS = 50 A. The current capability of the VCC regulator is also 50 mA, but the VCC tolerance is between 4.65V and 5.35V. If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible and the voltage regulator is switched off.
3.10
Wake Input Pin (WAKE)
This pin is a high voltage input used to wake the device up from Sleep Mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source with typically 10 A is implemented. If you don't need a local wake-up in your application, connect pin WAKE directly to pin VS.
3.11
MODE and TM Input Pins
These inputs are used for a special test mode of the watchdog in final production measurement at Atmel. In the application, they are always connected to GND. Wake-up events from Sleep Mode: * LIN bus * WAKE pin * EN pin
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3.12
Modes of Operation
Modes of Operation
Unpowered Mode, VBat = 0V
Figure 3-1.
b b
a b
Pre Normal Mode VCC: 5V/50 mA with undervoltage reset c+d Communication: OFF EN = 1 c+d EN = 0 TXD = 1 Local wake-up event Normal Mode VCC: 5V 2%/50 mA with undervoltage reset Communication: On EN = 0 EN = 0 TXD = 0 Local wake-up event EN = 1 a: VS > 5V b: VS < 4V c: Bus wake-up event d: Wake-up from wake-up switch Go to sleep command Sleep Mode VCC: switched off Communication: Off Go to silent command Normal Mode VCC: 5V 7%/50 mA with undervoltage reset Communication: OFF b
3.12.1
Normal Mode This is the normal transmitting and receiving mode. The voltage regulator is in normal mode and can source 50 mA. The undervoltage detection is activated. The watchdog needs a trigger signal from PTRIG or NTRIG to avoid resets at NRES.
3.12.2
Silent Mode A falling edge at EN while TXD is high switches the IC into Silent Mode. The TXD signal has to be logic high during the Mode Select window (Figure 3-2 on page 7). For EN and TXD either two independent outputs can be used, or two outputs from the same microcontroller port; in the second case, the mode change is only one command. In Silent Mode, the transmission path is disabled. Supply current from VBat is typically IVSsi = 40 A with no load at the VCC regulator. The overall supply current from VBat is the addition of 40 A plus the VCC regulator output current IVCCs.
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In Silent Mode, the 5V regulator is in low tolerance mode (4.65V to 5.35V) and can source up to 50 mA. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is shorted to GND. Only a weak pull-up current (typically 10 A) between pin LIN and pin VS is present. The Silent Mode voltage tolerance is sufficient to run the internal timers of the microcontroller. The undervoltage reset is now VccthS < 4.4V. If an undervoltage condition occurs, the NRES is switched to low and the ATA6621 changes state to Pre Normal Mode. A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period (Tbus) results in a remote wake-up request. The device switches from Silent Mode to Pre Normal Mode. The internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller. (Figure 3-5 on page 10) With EN high, you can switch directly from Silent Mode to Normal Mode. Figure 3-2. Switch to Silent Mode
Sleep Mode
EN
TXD
Mode Select window Td = 3.2 s
NRES
VCC
Delay time Sleep Mode Td_sleep = maximum 20 s LIN LIN switches directly to recessive mode
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Figure 3-3.
LIN Wake-up Waveform Diagram (from Silent Mode)
Pre Normal Mode Normal Mode
LIN bus
RXD
High Bus wake-up filtering time Tbus
Low
High
VCC Voltage Regulator
Silent Mode 4.5V to 5.5V/50 mA
Pre normal Mode 5V/50 mA
Normal Mode 5V/50 mA
Regulator Wake-up time EN Node In Silent Mode
EN High
NRES
If undervoltage, switch to Prenormal Mode
Undervoltage detection active
3.12.3
Sleep Mode A falling edge at EN while TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode Select window (Figure 3-4 on page 9), see section "Silent Mode" on page 6. In Sleep Mode the transmission path is disabled. Supply current from V Bat is typically IVSsleep = 10 A. The VCC regulator is switched off. NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is shorted to GND. Only a weak pull-up current (typically 10 A) between pin LIN and pin VS is present. A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period (Tbus) results in a remote wake-up request. The device switches from Sleep Mode to Pre Normal Mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller. (Figure 3-5 on page 10) With EN high you can switch directly from Silent Mode to Normal Mode. In the application where the ATA6621 supplies the microcontroller, wake-up from Sleep Mode is only possible via LIN or pin WAKE.
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Figure 3-4. Switch to Sleep Mode
Sleep Mode
EN
TXD
Mode Select window Td = 3.2 s
NRES
VCC
Delay time Sleep Mode Td_sleep = maximum 20 s LIN LIN switches directly to recessive mode
3.12.4
Pre Normal Mode At system power-up the device automatically switches to Pre Normal Mode. The voltage regulator is switched on VCC = 5V 2%/50 mA (see Figure 3-6 on page 12). The NRES output switches to low for tres = 10 ms and sends a reset to the microcontroller. LIN communication is switched off and the watchdog is active. The ATA6621 stays in this mode until EN is switched to high. If VBattery (VS < 4V) is powered down during Silent Mode or Sleep Mode, the IC powers up into Pre Normal Mode.
3.12.5
Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases due to the block capacitor (Figure 3-6 on page 12). When VS becomes higher than the VS undervoltage threshold VS_th, the IC mode changes from Unpowered Mode to Pre Normal Mode. The VCC output voltage reaches its nominal value after tVCC. This time depends on the VCC capacitor and the load. The NRES is low for the reset time delay treset. During this time, no mode change is possible.
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Figure 3-5.
LIN Wake-up Waveform Diagram from Sleep Mode
Pre Normal Mode Normal Mode
LIN bus
RXD
Low or floating Bus wake-up filtering time Tbus
Low
High
VCC Voltage Regulator
On state Off state Regulator Wake-up time Node ln operation EN High
EN
Node In Silent Mode Reset time
NRES
Low or floating Microcontroller start-up time delay
Table 3-1.
Mode of Operation Pre Normal Normal Silent Sleep
Table of Modes
Transceiver Off On Off Off VCC 5V 5V 5V 0V WD_OSC 2.5V 2.5V 0V 0V TEMP 2V 2V 0V 0V RXD 5V 5V 5V 0V LIN RECESSIVE RECESSIVE RECESSIVE RECESSIVE
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3.13
3.13.1
Wake-up Scenarios
Remote Wake-up via Dominant Bus State A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period (TBUS) results in a remote wake-up request. The device switches to Pre Normal Mode. The VCC voltage regulator is activated, and the internal slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to generate an interrupt in the microcontroller. The watchdog needs a trigger signal from PTRIG or NTRIG within the lead time tD to avoid resets at NRES. (Figure 3-2 on page 7) Local Wake-up via Pin Wake A falling edge at pin WAKE followed by a low level maintained for a certain time period (TWAKE) results in a local wake-up request. The extra long wake-up time (TWAKE) ensures that no transients as defined in ISO7637 create a wake-up. The device switches to Pre Normal Mode. The internal slave termination resistor is switched on. The local wake-up request is indicated by a low level at pin RXD to generate an interrupt in the microcontroller. The watchdog needs a trigger signal from PTRIG or NTRIG within the lead time tD to avoid resets at NRES. Wake-up Source Recognition The device can distinguish between a local wake-up request (pin WAKE) and a remote wake-up request (dominant LIN bus state). The wake-up source can be read on pin TXD in Pre Normal Mode. If an external pull-up resistor (typically 5 k) on pin TXD to the power supply of the microcontroller has been added, a high level indicates a remote wake-up request (weak pull down at pin TXD) and a low level indicates a local wake-up request (strong pull down at pin TXD). The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately, if the microcontroller sets pin EN to high (Figure 3-2 on page 7 and Figure 3-3 on page 8).
3.13.2
3.13.3
3.14
Fail-safe Features
* During a short circuit at LIN, the output limits the output current to IBUS_LIM. Due to the power dissipation, the chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. During LIN overtemperature switch-off, the VCC regulator works independently. * The reverse current at pin LIN is very low (< 3 A) during loss of VBAT or GND. This is optimal behavior for bus systems where some slave modes are supplied from battery or ignition. * During a short circuit at VCC, the output limits the output current to IVCCn. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Pre Normal Mode. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of Pre Normal Mode, the VCC voltage will switch on again although EN is switched off from the microcontroller. The microcontroller can start its normal operation. * Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. * Pin RXD is set floating if VBat is disconnected. * Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. * If the WD_OSC pin has a short circuit to GND or the resistor is disconnected, the watchdog oscillator runs with a high frequency and guarantees a reset in any condition. 11
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* The WD_OSC pin is a constant voltage regulator which supplies 2.5V for the external resistor ROSC to adjust the watchdog timing. This output is short circuit protected. A short circuit to GND causes a reset a pin NRES after typically 4 ms. An open circuit causes a reset at pin NRES after typically 7 ms.
3.15
Voltage Regulator
The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the microcontroller. It is recommend to use an electrolytic capacitor with C > 1.8 F and a tantalum capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application. During mode change from Silent to Normal Mode, the voltage regulator ramps up to 6V for only a few microseconds before it drops back to 5V. This behavior depends on the value of the load capacitor. With 4.7 F, the overshoot voltage has its greatest value. This voltage decreases with higher or lower load capacitors. The main power dissipation of the IC is created from the VCC output current IVCC , which is needed for the application. In Figure 3-7 on page 13 you see the safe operating range of the ATA6621. Figure 3-6.
VS
12V
VCC Voltage Regulator: Ramp Up and Undervoltage
5.5V
3V
t VCC
5V Vthun
tvcc
tres
tres_f
t
NRES
5V
t
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Figure 3-7. Power Dissipation: Safe Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures
55 50 45 40 Tamb = 105C
IVCC (mA)
Tamb = 125C
35 30 25 20 15 10 5 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
VS (V)
3.16
Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) or the PTRIG (positive edge) input within a period time window of Twd. The trigger signal must exceed a minimum time ttrigmin > 3 s. If a triggering signal is not received, a reset signal will be generated at output NRES. The timing basis of the watchdog is provided by the internal oscillator, of which the time period Tosc is adjustable via the external resistor Rwd_osc (10 k to 120 k). In Silent or Sleep Mode, the watchdog is switched off to reduce current consumption. Minimum time for first watchdog pulse is required after the undervoltage reset at NRES disappears and is defined as lead time td.
3.16.1
Typical Timing Sequence with Rwd_osc = 51 k The trigger signal Twd is adjustable between 2.9 ms and 33 ms via the external resistor Rwd_osc. For example, with an external resistor of Rwd_oscSC = 51 k 1%, the typical parameters of the watchdog come out as follows: tOSC = 12.5 s due to 51 k td = 3922 x 12.5 s = 49 ms t1 = 800 x 12.5 s = 10 ms t2 = 840 x 12.5 s = 10.5 ms tnres = 157 x 12.5 s = 1.96 ms
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After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES stays low for the time treset (typically 10 ms), then it switches to high and the watchdog waits for the watchdog sequence from the microcontroller. This lead time td follows after the reset and is td = 49 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger pulse NTRIG (or PTRIG, as the case may be) occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a watchdog reset with tNRES = 1.96 ms will reset the microcontroller after td = 49 ms. The times t1 and t2 have a fixed relationship with each other. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 10.5 ms. To avoid false triggering from glitches, the trigger pulse must be longer than ttrigg > 3 s. This slope serves to restart the watchdog sequence. Should the triggering signal fail in this open window t2, the NRES output will be drawn to ground after t2. A triggering signal during the closed window t1 causes NRES to immediately switch low. Figure 3-8.
VCC = 5V Undervoltage Reset NRES treset = 10 ms Watchdog Reset tnres = 1.9 ms
Timing Sequence with RWD_OSC = 51 k
td = 49 ms t1 = 10 ms twd t2 = 10.5 ms
t1
t2
NTRIG
PTRIG
ttrigg > 3 s
3.16.2
Worst Case Calculation with RWO_OSC = 51 k The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%. The worst case calculation for the watchdog period Twd the microcontroller has to provide is calculated as follows. The ideal watchdog time Twd is between (t1maximum) and (t1 minimum plus t2 minimum). t1,min = 0.8 x t1 = 8 ms, t1,max = 1.2 x t1 = 12 ms t2,min = 0.8 x t2 = 8.4 ms, t2,max = 1.2 x t2 = 12.6 ms Twdmax = t1min + t2min = 8 ms + 8.4 ms = 16.4 ms Twdmin = t1max = 12 ms Twd = 14.2 ms 2.2 ms (15%) A microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly within the time period of Twd = 14.2 ms (15%) in an application with Rwd_osc = 51 k.
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Table 3-2.
Rwd_osc k 10 51 91 120
Table of Watchdog Timings
Oscillator Period tosc/s 2.6 12.5 22.4 29 Lead Time td/ms 10.2 49.4 87.8 113.7 Closed Window t1/ms 2.08 10 17.92 23.2 Open Window t2/ms 2.18 10.5 18.82 24.36 Trigger Period from microcontroller Reset time twd/ms tnres/ms 2.90 14.2 25.45 32.94 0.41 1.96 3.52 4.55
3.17
Temperature Monitor at Pin TEMP
In addition to the internal temperature monitoring of the voltage regulator, an additional sensor measures the junction temperature and provides a linearized voltage at the TEMP pin. Together with the analog functions of the microcontroller (for example, the analog comparator and the Analog-to-digital converter (ADC)), this enables the application to detect overload conditions and to take corresponding measures in order to prevent damage. An external capacitor buffers the voltage due to the input current of the ADC. The sensor itself is built out of three diodes which are supplied by an internal BIAS current in Pre Normal Mode and Normal Mode. The typical voltage at T = 27C is Vtemp = 2.2V with a typical negative temperature coefficient of VTC,TEMP = -5.4 mV/k. Figure 3-9. Temperature Monitor
VCC 20 A TEMP
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters VS - Continuous supply voltage - Transient voltage (load dump) WAKE DC and transient voltage (with 33 k serial resistor) Transient voltage due to ISO7637 (coupling 1 nF) Logic pins (RXD, TXD, EN, NRES, PTRIG, NTRIG, PVCC, WD_OSC, TEMP) LIN - DC voltage - Transient voltage VCC DC voltage ESD (DIN EN 6100-4-2) According LIN EMC Test Specification 1.3 - Pin VS, LIN to GND - Pin WAKE (33 k serial resistor) ESD HBM - All pins according to ESD S 5.1 CDM ESD STM 5.3.1-1999 - All pins Junction temperature Storage temperature Operating ambient temperature Thermal resistance junction to heat slug Thermal resistance junction to ambient, where heat slug is soldered to PCB Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Tj Ts Ta Rthjc Rthja 150 150 35 165 165 10 170 170 Symbol Min -0.3 Typ Max +40 +44 +40 +100 +6.5 Unit
V
-40 -150 -0.3
V V
-40 -150 -0.3
+60 +100 6.5
V
V
6 5 2 1 -40 -55 -40 +150 +150 +125 10
KV KV KV KV C C C K/W K/W C C C
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5. Electrical Characteristics
5V < VS < 18V, Tamb = -40C to +125C No. 1 1.1 Parameters VS Pin Nominal DC voltage range Supply current in Sleep Mode Supply current in Silent Mode Sleep Mode Vlin >VBat - 0.5V VBat < 14V (25C to 125C) Bus recessive; VBat < 14V (25C to 125C) Without load at VCC VS IVSsleep 5 18 V A Test Conditions Pin Symbol Min Typ Max Unit Type*
1.2
10
20
A
A
1.3
IVSsi IVSrec IVSdom VSth VSth_hys 4.0
40
55
A
A
1.4 1.5 1.6 1.7 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4
Supply current in Normal Bus recessive Mode Without load at VCC Supply current in Normal Bus dominant Mode VCC load current 50 mA VS undervoltage threshold VS undervoltage threshold hysteresis RXD Output Pin Low-level input current Normal Mode; VLIN = 0V VRXD = 0.4V
4 55 4.5 0.2 5
mA mA V V
A A A A
IRXD VRXDL RRXD
2
5
8 0.4
mA V k
A A A
Low-level output voltage IRXD = 1 mA Internal 5 k resistor to VCC TXD Input Pin Low-level voltage input High-level voltage input Pull-up resistor High-level leakage current VTXD = 0V VTXD = 5V
3
7
VTXDL VTXDH RTXD ITXD
-0.3 3.5 125 -3 250
+1.5 VCC + 0.3V 600 +3
V V k A
A A A A
3.5
Pre Normal Mode; Low-level input current at VLIN = VBattery VWAKE = 0V local wake-up request VTXD = 0.4V
ITXDwake
2
5
8
mA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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5. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = -40C to +125C No. 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 7 7.1 7.2 7.3 Parameters EN Input Pin Low-level voltage input High-level voltage input Pull-down resistor Low-level input current NRES Output Pin High-level output voltage Low-level output voltage Low-level output low Undervoltage reset time VS 5.5V; Inres = -1 mA VS 5.5V; Inres = -1 mA 10 k to VCC; VCC = 0.8V VVS 5.5V CNRES = 20 pF VNRESH VNRESL VNRESLL treset tres_f 7 4.2 0.4 0.3 13 5 V V V ms s A A A A A VEN = 5V VEN = 0V VENL VENH REN IEN -0.3 3.5 125 -3 250 +1.5 VCC + 0.3V 600 +3 V V k A A A A A Test Conditions Pin Symbol Min Typ Max Unit Type*
Reset debounce time for VVS 5.5V CNRES = 20 pF falling edge Voltage Regulator VCC Pin in Normal and Pre Normal Mode Output voltage VCC Output voltage VCC at low VS Regulator drop voltage Regulator drop voltage Regulator drop voltage Output current Load capacity VCC undervoltage threshold Hysteresis of undervoltage threshold 5.5V < VS < 18V (0 mA to 50 mA) 3.3V < VS < 5.5V VS > 4.0V, IVCC = -20 mA VS > 4.0V, IVCC = -50 mA VS > 3.3V, IVCC = -15 mA VS > 3V 1 < ESR < 5 Referred to VCC VS > 5.5V Referred to VCC VS > 5.5V
VCCnor VCClow VD1 VD2 VD3 IVCC IVCCs Cload VthunN Vhysthun tVCC
4.9 VVS - VD
5.1 5.1 250 500 200
V V mV mV mV mA mA F
A A A A A A A D A A A
-50 -200 1.8 4.4 40 1 2 -130 2.2 4.8
Output current limitation VS > 0V
V mV ms
Ramp up time VS > 5.5V CVCC = 2.2 F to VCC > 4.9V Rload at VCC: 100 Voltage Regulator VCC Pin in Silent Mode Output voltage VCC Output voltage VCC at low VS Regulator drop voltage 5.5V < VS < 18V (0 mA to 50 mA) 3.3V < VS < 5.5V VS > 3.3V, IVCC = -15 mA
VCCnor VCClow VD
4.65 VVS - VD
5.35 5.1 200
V V mV
A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
18
ATA6621
4887B-AUTO-01/06
ATA6621
5. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = -40C to +125C No. Parameters At VCC undervoltage threshold the state switches back to Pre Normal Mode Hysteresis of undervoltage threshold Test Conditions Referred to VCC VS > 5.5 Referred to VCC VS > 5.5V Pin Symbol Min Typ Max Unit Type*
7.4
VthunS
3.9
4.4
V
A
7.5 7.6 8
Vhysthun IVCCs
40 -200 -130
mV mA
D A
Output current limitation VS > 0V
LIN Bus Driver: Bus Load Conditions: Load1 (Small): 1 nF, 1 k; Load2 (Large): 10 nF, 500; RRXD = 5 k; CRXD = 20 pF 10.5, 10.6 and 10.7 Specify the Timing Parameters for Proper Operation at 20 Kbps Driver recessive output voltage Driver dominant voltage Driver dominant voltage Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage Pull-up resistor to VS Self-adapting current limitation VBus = VBatt_max Input leakage current at the receiver including pull-up resistor as specified Leakage current LIN recessive Load1 / Load2 VVS = 7V Rload = 500 VVS = 18V Rload = 500 VVS = 7V Rload = 1000 VVS = 18V Rload = 1000 The serial diode is mandatory Tj = 125C Tj = 27C Tj = -40C Input leakage current Driver off VBUS = 0V VBattery = 12V Driver off 8V < VBattery < 18V 8V < VBUS < 18V VBUS VBatt VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k_ RLIN IBUS_LIM 0.6 0.8 20 52 80 120 30 60 110 170 230 0.9 VS VS 1.2 2 V V V V V k mA mA mA A A A A A A A
8.1 8.2 8.3 8.4 8.5 8.6 8.7
8.8
IBUS_PAS_dom
-1
mA
A
8.9
IBUS_PAS_rec
15
20
A
A
8.10
Leakage current when control unit disconnected GNDDevice = VS from ground. Loss of VBattery = 12V local ground must not 0V < VBUS < 18V affect communication in the residual network Node has to sustain the current that can flow VBattery disconnected under this condition. Bus VSUP_Device = GND must remain operational 0V < VBUS < 18V under this condition
IBUS_NO_gnd
-10
0.5
10
A
A
8.11
IBUS
0.5
3
A
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
19
4887B-AUTO-01/06
5. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = -40C to +125C No. 9 9.1 9.2 9.3 9.4 9.5 9.6 10 10.1 Parameters LIN Bus Receiver Center of receiver threshold VBUS_CNT = (Vth_dom + Vth_rec) / 2 VBUS_CNT VBUSdom VBUSrec VBUShys VLINH Initializes a wake-up signal VLINL 0.475 VS -27 0.6 VS 0.028 VS VS - 1V -27 0.1 VS 0.5 VS 0.525 - VS 0.4 VS 40 0.175 VS VS + 0.3V VS - 3.3V V V V V V V A A A A A A Test Conditions Pin Symbol Min Typ Max Unit Type*
Receiver dominant state VEN = 5V Receiver recessive state VEN = 5V Receiver input hysteresis VHYS = Vth_rec - Vth_dom Wake detection LIN High-level input voltage Wake detection LIN Low-level input voltage Internal Timers Dominant time for wakeVLIN = 0V up via LIN bus Time delay for mode change from Pre Normal VEN = 5V to Normal Mode via pin EN Time delay for mode change from Normal into VEN = 0V Sleep Mode via pin EN TXD dominant time-out timer VTXD = 0V THRec(max) = 0.744 x VS; THDom(max) = 0.581 x VS; VS = 7.0V to 18V; tBit = 50 s D1 = tbus_rec(min) / (2 x tBit) THRec(min) = 0.422 x VS; THDom(min) = 0.284 x VS; VS = 7.0V to 18V; tBit = 50 s D2 = tbus_rec(max) / (2 x tBit) Slope time dominant and recessive edges VWAKE = 0V
Tbus
30
90
150
s
A
10.2
Tnorm
5
15
20
s
A
10.3
Tsleep Tdom
2
7
12
s
A
10.4
5
10
20
ms
A
10.5
Duty cycle 1
D1
0.396
A
10.6
Duty cycle 2
D2
0.581
A
10.7 10.8 11 11.1
Slope time falling and rising edge at LIN Time of low pulse for wake-up via pin WAKE Propagation delay of receiver (Figure 5-1 on page 22)
TSLOPE_fall TSLOPE_rise TWAKE
3.5 60 130
22.5 200
s s
A A
Internal Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions (CRXD): 20 pF trec_pd = max(trx_pdr, trx_pdf) trx_pd 6 s A
11.2
Symmetry of receiver propagation delay rising trx_sym = trx_pdr - trx_pdf edge minus falling edge
trx_sym
-2
2
s
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
20
ATA6621
4887B-AUTO-01/06
ATA6621
5. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = -40C to +125C No. 12 12.1 12.2 12.3 13 13.1 13.2 13.3 13.4 13.5 13.6 14 14.1 14.2 14.3 14.4 15 15.1 Parameters Watchdog input highlevel threshold Watchdog input low threshold Internal pull down PTRIG Internal pull down PTRIG Watchdog Oscillator Voltage at WD_OSC in Normal Mode Possible values of resistor Oscillator period Oscillator period Oscillator period Oscillator period Watchdog lead time after reset Watchdog closed window Watchdog open window Watchdog reset time NRES Temperature Monitor at Pin TEMP Voltage at TEMP in Normal Mode (T = -40C) ITEMP = 3 A VTEMP VTEMP VTEMP ITEMP VTC,TEMP VWAKEH Initializes a wake-up signal VS < 27V, VWake = 0V VS = 27V; VWake = 27V VWAKEL IWAKE IWAKEL VS - 1V -27 -30 -5 -10 +5 2.35 2.7 V A ROSC = 10 k ROSC = 51 k ROSC = 91 k ROSC = 120 k IWD_OSC = -250 A VWD_OSC ROSC tOSC tOSC tOSC tOSC 2.3 10 2.1 10 17.9 23.2 2.6 12.5 22.4 29 2.5 2.7 120 3.1 15 26.8 34.8 V k s s s s A A A A A A Test Conditions Pin Symbol Min Typ Max Unit Type* Watchdog Input PTRIG and NTRIG V_HPTRIG V_LPTRIG RpdPTRIG RpuNTRIG 125 3.5 1.5 200 V V k A A A
Watchdog Timing Relative to tOSC td t1 t2 tnres 3922 800 840 157 cycles cycles cycles cycles A A A A
15.1
Voltage at TEMP in = 3 A I Normal Mode (T = 27C) TEMP Voltage at TEMP in Normal Mode (T = 125C) Short current at TEMP Temperature gradient Wake Pin High-level input voltage Low-level input voltage Wake pull-up current High-level leakage current ITEMP = 3 A VTEMP = 0V
2.0
2.35
V
A
15.1 15.2 15.3 16 16.1 16.2 16.3 16.4
1.4 -30 -5.4
1.9 -15
V A mV/k
A A C A A A A
VS + 0.3V VS - 3.3V
V V A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
21
4887B-AUTO-01/06
Figure 5-1.
Definition of Bus Timing Parameters
tBit tBit tBit
TXD (input to transmitting node)
tBus_dom(max)
tBus_rec(min)
THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min)
Thresholds of receiving node1
Thresholds of receiving node2
tBus_dom(min)
tBus_rec(max)
RXD (output of receiving node1) trx_pdf(1) trx_pdr(1)
RXD (output of receiving node2) trx_pdr(2) trx_pdf(2)
22
ATA6621
4887B-AUTO-01/06
ATA6621
Figure 5-2. Application Circuit
VBattery 22 F
+
100 nF 1 nF PVCC TEMP
Master node pull-up
10 k
VS
100 nF
+ 10 F
GND
VCC
1 k
20
19
18
17
16 15
EN VCC PTRIG NTRIG
1
MODE TM WD_OSC NRES TXD 10 k LIN sub bus 220 pF
ATA6621
2 3 4 5 6 7 8 9 10 MLP 5 mm x 5 mm 0.65 mm pitch 20 lead 14 13 12 11
Microcontroller
33 k
WAKE GND
EN PTRIG
Wake-up switch
NC
LIN
NC
NTRIG RXD TXD RESET
RXD
NC
23
4887B-AUTO-01/06
Figure 5-3.
Application Circuit with External NPN
VBattery 100 F + 100 nF MJD31C
+
Master node pull-up 1 nF
2.2 F 100 nF
+ 10 F
PVCC
TEMP
VS
10 k
20
19
18
17
GND
VCC
3
1 k
16 15
EN VCC PTRIG NTRIG
1
MODE TM WD_OSC NRES TXD 10 k LIN sub bus 220 pF
4887B-AUTO-01/06
ATA6621
2 3 4 5 6 7 8 9 10 MLP 5 mm x 5 mm 0.65 mm pitch 20 lead 14 13 12 11
Microcontroller
33 k
WAKE GND
EN PTRIG
Wake-up switch
RXD
NC
LIN
NC
NTRIG RXD TXD RESET
24
ATA6621
NC
ATA6621
6. Ordering Information
Extended Type Number ATA6621-PGQW Package QFN20 Remarks Pb-free
7. Package Information
25
4887B-AUTO-01/06
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4887B-AUTO-01/06

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